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I received a B.S. in electrical engineering from the California Institute of Technology in 2000, and a M.S. and Ph.D. in electrical & computer engineering from Cornell University in 2002 and 2004, where I was an NSF fellow.
I work in the Microsystems Center at Sandia National Laboratories.
VLSI design is my primary professional interest, and most of my publications are listed below.
I like to hike the Sandia Mountains in my spare time, and hiked the La Luz trail in 2005.
Recent Papers:
John Teifel.
Asynchronous Cryptographic Hardware Design.
IEEE International Carnahan Conference on Security Technology,
October 2006.
John Teifel, R.S. Flores, K.K. Ma.
Asynchronous Logic Design for Rad-Hard Structured ASICs.
Government Microcircuit Applications & Critical Technology Conference,
March 2006.
John Teifel.
Hardening Low-Power Asynchronous Control Circuits.
IEEE Nuclear and Space Radiation Effects Conference,
July 2005.
GHz Asynchronous FPGA Papers:
David Fang, John Teifel, and Rajit Manohar.
A High-Performance Asynchronous FPGA: Test Results.
IEEE Symposium on Field-Programmable Custom Computing Machines,
April 2005.
Song Peng, David Fang, John Teifel, and Rajit Manohar.
Automated Synthesis for Asynchronous FPGAs.
13th ACM International Symposium on Field-Programmable Gate Arrays,
February 2005.
John Teifel and Rajit Manohar.
An Asynchronous Dataflow FPGA Architecture.
IEEE Transactions on Computers (special issue), 53(11):1376-1392, November 2004.
John Teifel.
Fast Prototyping of Asynchronous Logic.
Ph.D. dissertation, Cornell University, August 2004.
(Nominated for 2004 ACM Doctoral Dissertation Award)
John Teifel and Rajit Manohar.
Highly Pipelined Asynchronous FPGAs.
12th ACM International Symposium on
Field-Programmable Gate Arrays,
February 2004.
John Teifel and Rajit Manohar.
Programmable Asynchronous Pipeline Arrays.
13th International
Conference on Field Programmable Logic and Applications,
September 2003.
Fine-grain QDI Pipeline Papers:
John Teifel and Rajit Manohar.
Static Tokens: Using Dataflow to
Automate Concurrent Pipeline Synthesis.
10th IEEE International Symposium
on Asynchronous Circuits and Systems,
April 2004.
John Teifel and Rajit Manohar.
A High-Speed Clockless Serial Link Transceiver.
9th IEEE International Symposium
on Asynchronous Circuits and Systems,
May 2003.
John Teifel.
Interchip Communication in Asynchronous VLSI Systems.
M.S. thesis, Cornell University, May 2002.
John Teifel, David Fang, David Biermann, Clint Kelly, and Rajit
Manohar.
Energy-Efficient Pipelines.
8th IEEE International Symposium on Asynchronous Circuits and Systems,
April 2002.
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